Phase interpolators may be used to provide phase control of a clock signal. A phase interpolator receives multiple input clock signals, each having a different phase. The phase interpolator mixes two of the incoming clock phases to generate an output clock signal having a programmable phase. For example, two input clock signals may be provided to a phase interpolator, one having a 0 degree phase, and one having a 90 degree phase. The phase interpolator may then output a clock signal having a phase between 0 and 90 degrees. The phase interpolator includes a mixer which may weigh the input clock signals and combine them to generate the output signal having the programmable phase.
For a larger range, a phase interpolator may select between multiple input signals. For example, input clock signals having a 0 degree phase, a 90 degree phase, a 180 degree phase, and a 270 degree phase may be available to a phase interpolator. A selector may be provided to select the input clock signals provided to the phase interpolator. When the 0 degree phase and 90 degree phase signals are selected, the phase interpolator may generate an output clock signal having a programmable output phase between 0 and 90 degrees. When the 90 degree phase and 180 degree phase input signals are selected, the phase interpolator may generate an output clock signal having a programmable output phase between 90 and 180 degrees.
One metric used to describe phase interpolators is their linearity. To improve the linearity of the placement of the phase of the programmable output clock signal, current mode logic buffers have been used to provide the input clock signals to a phase interpolator circuit containing a buffer. The current mode logic buffers may improve the linearity of operation of the phase interpolator circuit.
FIG. 1 is a schematic illustration of a current mode logic buffer. The current mode logic buffer 100 may receive a differential clock signal, INN and INP and output a differential output signal OUTN and OUTP. The INN and INP input clock signals may be provided to gates of n-FET transistors 105 and 107 respectively. Load resistors 110 and 112 are coupled to drain terminals of the transistors 105 and 107, respectively. A transistor 120 is coupled to the source terminals of the transistors 105 and 107. The transistor 120 receives a bias voltage BN at its gate terminal and may draw a corresponding amount of current from the transistors 105 and 107.
The INP signal may turn on the transistor 107, allowing current flow through the resistor 112 and generating the OUTN signal. The INN signal may turn on the transistor 105, allowing current flow through the resistor 110 and generating the OUTP signal.
FIG. 2 is an example graph illustrating an output signal, from a current mode logic buffer. The graph illustrates the voltage of the OUTN signal over tune. The resistances 112 and 110 of the current mode logic buffer 100 in FIG. 1 create an RC effect on the output waveform. The output signal 210 is illustrated in FIG. 2, and the RC effect generated by the resistances 112 and 110 can be seen by the variation in slope of the output signal.